CPU: wiring the control bits

01What the CPU does: 16 bits onto control pins

The CPU invents nothing. It does one thing: split the fetched 16-bit instruction into control signals and drive the control pins of the ALU, registers, memory and PC.

The format (how A and C instructions are written) is on the machine language page; what the machine promises externally is on the Hack computer page. This page cares about one thing: how those bits become wires.

02Where the six control bits come from

Bits 11–6 of a C instruction are in exactly the same order as the ALU’s six control bits:

That is why the ALU page presents them in the order zx nx zy ny f no: it matches the instruction exactly, so wiring is one bit to one pin with no conversion.

03Datapath: x is always D, y follows the a bit

The ALU’s two inputs are not arbitrary:

• x = the D register: hard-wired, so every instruction implicitly computes with D.
• y = A or M: chosen by the a bit. When it picks M, M is RAM[A] — A doubles as the address.

Writing back uses three independent lines: d1 writes A, d2 writes D, d3 writes M (each gated by “this is a C instruction”).So the number of combinations on the left of = in D=M+1 is the number of control lines.

04Jumps: three bits plus two flags

The last three bits j1 j2 j3 mean “less / equal / greater”. ANDed with the ALU flags ng (negative) and zr (zero), they produce “jump or not”:

Note: 0;JMP has no destination — the result is only tested, not written back anywhere.

05One instruction, step by step

One pass per clock tick. A “program” is just these 16-bit words lined up in memory.

06How PC gets written

PC is not a register programs write directly; it has three inputs, in priority order:

So a jump is two wires in hardware: send A to the PC input, then raise load.An A instruction puts the target address into A first; only then can a jump mean anything.

The jump condition is the three jump bits ANDed/ORed with the ALU’s zr / ng — load goes high only when it holds.When it does not hold, load=0 and PC still increments.

07Writing it in HDL

// Hack CPU: A and D registers + ALU + PC
CHIP CPU {
  IN inM[16], instruction[16], reset;
  OUT outM[16], writeM, addressM[15], pc[15];

  PARTS:
  // A input: an A-instruction writes a constant, a C-instruction writes the ALU result
  Mux16(a=instruction, b=aluOut, sel=instruction[15], out=aIn);
  Not(in=instruction[15], out=notInstruction);

  // A register: always written by an A-instruction; a C-instruction looks at d1
  Or(a=notInstruction, b=instruction[5], out=loadA);
  ARegister(in=aIn, load=loadA, out=aOut, out[0..14]=addressM);

  // ALU y: the a bit picks A or M
  Mux16(a=aOut, b=inM, sel=instruction[12], out=yIn);

  // ALU control: on an A-instruction, pass D through (zy=ny=1, f=0 → D ∧ -1)
  And(a=instruction[11], b=instruction[15], out=zx);
  And(a=instruction[10], b=instruction[15], out=nx);
  Or(a=instruction[9],  b=notInstruction, out=zy);
  Or(a=instruction[8],  b=notInstruction, out=ny);
  And(a=instruction[7], b=instruction[15], out=f);
  And(a=instruction[6], b=instruction[15], out=no);

  ALU(x=dOut, y=yIn,
      zx=zx, nx=nx, zy=zy, ny=ny, f=f, no=no,
      out=outM, out=aluOut, zr=zr, ng=ng);

  // write memory: only a C-instruction with d3
  And(a=instruction[15], b=instruction[3], out=writeM);

  // D register: only a C-instruction with d2
  And(a=instruction[15], b=instruction[4], out=loadD);
  DRegister(in=aluOut, load=loadD, out=dOut);

  // jump: j1 = less, j2 = equal, j3 = greater
  Or(a=zr, b=ng, out=notPos);
  Not(in=notPos, out=pos);
  And(a=instruction[0], b=pos, out=jgt);
  And(a=instruction[1], b=zr,  out=jeq);
  And(a=instruction[2], b=ng,  out=jlt);
  Or(a=jgt, b=jeq, out=j1);
  Or(a=j1, b=jlt, out=jCond);
  And(a=jCond, b=instruction[15], out=jump);

  // PC: load A on a jump, otherwise increment
  PC(in=aOut, load=jump, reset=reset, inc=true, out[0..14]=pc);
}

Three things to notice in this code: every control bit comes from instruction[..] (a few are gated), and there is no separate decoder; A is both data and address; the PC load comes from the jump logic.